During the manufacture of dynamic random access memories ("DRAMs"), it is useful to test the DRAM to assure that it is operating properly. Electronic systems containing DRAMs, such as computers, normally test the DRAMs when power is initially applied to the system. A DRAM is typically arranged as an array of individual memory cells. In order to assure that each memory cell is operating properly, prior art test methods write data having a first binary value (e.g., a 1) to all memory cells in the memory array. For a memory array having n rows and m columns of memory cells, it requires n.times.m bus cycles to write the first binary data values to all the memory cells in the memory array. A bus cycle is the period of time it takes to write or read data to or from an individual memory cell in the DRAM. After having written the first binary data values to the memory cells, this data must be read from the memory cells to assure that each memory cell is operating properly. Once again, this requires n.times.m bus cycles to read the data having a first binary value. Data having a second binary value (e.g., a 0) is next written to each memory cell in the memory array and is then read from each memory cell to assure each memory cell is operating properly. Each of these read and write operations also requires n.times.m bus cycles to complete. Therefore, to test each memory cell in the memory array, a total of four times n.times.m bus cycles is required. In the case of a 64 megabit DRAM organized in a.times.4 input output configuration, 67,108,864 bus cycles are required to perform a complete test of every memory cell.
As will be appreciated by one skilled in the art, the greater the number of bus cycles required to test all memory cells in a DRAM, the greater the time it takes to test the DRAM. Thus, it is desirable to reduce the number of bus cycles required to test all the memory cells of a DRAM.